• 专利附录
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  • 法律状态
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    • 专利摘要:
    An output buffer circuit is disclosed that can reduce an average current consumption and prevent malfunction due to noise. The source of the first PMOS transistor is connected to the power supply terminal, the drain is connected to the output terminal of the output buffer circuit, and is turned on when a high level signal is input to the input terminal of the output buffer circuit. The source of the first NMOS transistor is connected to the ground terminal, the drain is connected to the output terminal of the output buffer circuit, and is turned on when a low level signal is input to the input terminal of the output buffer circuit. When a high level signal is received at an input terminal of the output buffer circuit, the low pulse generator generates a low pulse for a predetermined period immediately after the high level signal is received. When the low pulse signal is received at the input terminal of the output buffer circuit, the high pulse generator generates a high pulse for a predetermined period immediately after the low level signal is received. A source of the second PMOS transistor is connected to a power supply terminal, a drain thereof is connected to a drain of the first PMOS transistor, and an output signal of a low pulse generator is applied to a gate. A source of the second NMOS transistor is connected to the ground terminal, a drain is connected to the drain of the first NMOS transistor, and an output signal of the high pulse generator is applied to the gate.
    公开号:KR20030060176A
    申请号:KR1020020000713
    申请日:2002-01-07
    公开日:2003-07-16
    发明作者:정회권
    申请人:주식회사 하이닉스반도체；
    IPC主号:
    专利说明:

    Output buffer circuit {AN OUTPUT BUFFER CIRCUIT}
    [7] The present invention relates to an output buffer circuit, and more particularly to an output buffer circuit having a noise improvement effect. Although the present invention can be particularly usefully applied to semiconductor memory devices, it can be applied to all kinds of semiconductor devices.
    [8] The output buffer circuit of the semiconductor memory device includes a pull-up transistor and a pull-down transistor having a large size to drive a capacitive load outside the chip. Therefore, when 16 input / output lines (hereinafter referred to as “I / O”) simultaneously perform read operations in the semiconductor memory device, very large noise may be generated by the output buffer circuit, thereby causing malfunction.
    [9] 1 is a circuit diagram of a conventional output buffer circuit. The output buffer circuit 100 shown in FIG. 1 is a CMOS type consisting of a PMOS pull-up transistor P1 and an NMOS pull-down transistor N1. The output buffer circuit 100 is enabled when the pulsed output enable signal (hereinafter referred to as "poe") is at a high level, and the sense amplifier output signal (hereinafter referred to as "saout"). Is a high level, a low level signal is applied to node dp1 by block 102, and a low level signal is applied to node dn1 by block 104. " Therefore, the PMOS pull-up transistor P1 is turned on, the NMOS pull-down transistor N1 is turned off, and a high level signal is output from the output terminal dout1. On the other hand, when the sense amplifier output signal saout is low level, the high level signal is applied to the node dp1 by the block 102 and the high level signal is applied to the node dn1 by the block 104. Accordingly, the PMOS pull-up transistor P1 is turned off, the NMOS pull-down transistor N1 is turned on, and a low level signal is output from the output terminal dout1.
    [10] In the output buffer circuit 100, the PMOS pull-up transistor P1 and the NMOS pull-down transistor N1 are configured as transistors having a large size to drive the capacitive load of the output terminal dout1 at high speed. Therefore, when a read operation is simultaneously performed on 16 I / 0s of a semiconductor memory device, a large amount of current flows for a short time, and a large noise is generated, which is likely to cause a malfunction of the semiconductor memory device.
    [11] The present invention has been proposed to solve such a problem, and an object of the present invention is to provide an output buffer circuit that can prevent malfunction due to noise by reducing the average current consumption while maintaining the speed of the output buffer circuit.
    [1] 1 is a circuit diagram of a conventional output buffer circuit.
    [2] 2 is a circuit diagram of an output buffer circuit according to an embodiment of the present invention.
    [3] 3 is a voltage waveform diagram of the circuit of FIG. 1;
    [4] 4 is a voltage waveform diagram of the circuit of FIG. 2;
    [5] 5 is a diagram of current waveforms at an output terminal of the circuit of FIG. 1;
    [6] 6 is a diagram of current waveforms at an output terminal of the circuit of FIG. 2;
    [12] In order to achieve the above object, the present invention provides an output buffer circuit in which a source is connected to a power supply terminal, a drain is connected to an output terminal of the output buffer circuit, and a high level signal is input to an input terminal of the output buffer circuit. A first PMOS transistor that is turned on when the source is connected to a ground terminal, a drain is connected to an output terminal of the output buffer circuit, and is turned on when a low level signal is input to an input terminal of the output buffer circuit An NMOS transistor is provided. In addition, when a high level signal is received at an input terminal of the output buffer circuit, a low pulse generator for generating a low pulse for a predetermined period immediately after the high level signal is received, and a low level at an input terminal of the output buffer circuit. When the signal of the level is received, a high pulse generator for generating a high pulse for a predetermined period immediately after the low-level signal is received. In addition, the source is connected to a power supply terminal, the drain is connected to the drain of the first PMOS transistor, the gate is a second PMOS transistor to which the output signal of the low pulse generator is applied, the source is connected to the ground terminal, the drain is A second NMOS transistor is connected to the drain of the first NMOS transistor, and has a gate to which an output signal of the high pulse generator is applied.
    [13] The low pulse generator includes a first inverter for inverting a signal applied to the drain of the first PMOS transistor, an input terminal is connected to the gate of the first PMOS transistor, and a non-inverting control terminal is connected to the drain of the first PMOS transistor. The inverting control terminal is connected to a first transmission gate connected to an output terminal of the first inverter, a second inverter for inverting an output signal of the first transmission gate, an output signal of the second inverter, and the first inverter. And a first logic means for performing an OR operation on the signal applied to the gate of the PMOS transistor, and outputting the operation result as an output signal of the low pulse generator. The high pulse generator is configured to invert a signal applied to the drain of the first NMOS transistor, an input terminal is connected to a gate of the first NMOS transistor, and an inversion control terminal is connected to a drain of the first NMOS transistor. The non-inverting control terminal is connected to a second transmission gate connected to an output terminal of the first inverter, a fourth inverter for inverting an output signal of the second transmission gate, an output signal of the fourth inverter, and the first inverter. And a second logic means for performing an OR operation on the signal applied to the gate of the first NMOS transistor and outputting the operation result as an output signal of the high pulse generator.
    [14] The first PMOS transistor is composed of a PMOS transistor having a smaller size than the conventional PMOS pull-up transistor, and the first NMOS transistor is preferably composed of an NMOS transistor having a relatively smaller size than a conventional NMOS pull-down transistor.
    [15] According to the configuration of the present invention as described above, the current flowing to the pull-up PMOS transistor and the pull-down NMOS transistor can be reduced by about 10% while maintaining the driving speed as compared with the conventional output buffer circuit. As a result, when 16 I / Os simultaneously perform a READ operation, noise may be generated due to a high current, thereby preventing malfunction of the semiconductor memory device.
    [16] Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention; In the drawings, the same reference numerals are used to refer to the same or similar components and signals for the sake of consistency of description.
    [17] 2 is a circuit diagram of an output buffer circuit according to an embodiment of the present invention. As shown in FIG. 2, the output buffer circuit 200 includes a high level signal path 202, a pull-up transistor unit 204, a feedback low pulse generator 206, a low level signal path 210, and a pull-down transistor. The unit 212 and the feedback high pulse generator 214 are main components.
    [18] As shown in Fig. 2, the high level signal path 202 includes a NAND gate I11 having two input signals as a sense amplifier output signal saout and a pulsed output enable signal poe, and a NAND gate. An inverter I12 for inverting the output signal of I11 and an inverter I13 for inverting the output signal of the inverter I12. The high level signal path 202 causes the high level sense amplifier output signal saout to be applied to the node dp2 at a low level when the enable signal poe is at a high level, thereby turning on the PMOS pull-up transistor P11. Be sure to In contrast, the low level signal path 210 has two input signals, an inverter I14 that inverts the sense amplifier output signal saout, an output signal of the inverter I14, and a pulsed output enable signal poe. NAND gate I15 and inverter I16 which inverts the output signal of NAND gate I15. The low level signal path 210 causes the low level sense amplifier output signal saout to be applied to the node dn2 at a high level when the enable signal poe is at a high level so that the NMOS pull-down transistor N11 is turned on. Be sure to
    [19] The pull-up transistor unit 204 is composed of two PMOS transistors P11 and P12. A source voltage Vcc is provided to a source of the PMOS transistor P11, a signal of the node dp2 is applied to a gate, and a drain thereof is connected to an output terminal dout2 of the output buffer 200. The size of the PMOS transistor P11 is 1/2 of the size of a conventional pull-up PMOS transistor. A source voltage Vcc is provided to the source of the PMOS transistor P12, a signal of the node pp2 is applied to the gate, and a drain is applied to the output terminal dout2 of the output buffer 200 similarly to the PMOS transistor P11. It is connected. The pull-up transistor unit 204 is controlled by a signal applied to the node dp2 and a signal applied to the node pp2 to pull up the output terminal dout2 to the power supply voltage Vcc. In contrast, the pull-down transistor unit 212 includes two NMOS transistors N11 and N12. A source of the NMOS transistor N11 is provided with a ground voltage Vss, a gate signal is applied to the node dn2, and a drain thereof is connected to the output terminal dout2 of the output buffer 200. The size of the NMOS transistor N11 is 1/2 of the size of a conventional pull-down NMOS transistor. A source of the PMOS transistor N12 is provided with a ground voltage Vss, a gate signal is applied to the node nn2, and a drain is applied to the output terminal dout2 of the output buffer 200 similarly to the NMOS transistor N11. It is connected. The pull-down transistor unit 212 is controlled by a signal applied to the node dn2 and a signal applied to the node nn2 to pull down the output terminal dout2 to the ground voltage Vss.
    [20] The feedback low pulse generator 206 includes three inverters I21, I22, and I24, a transfer gate 208, and a NOR gate 123. The inverter I21 inverts the signal applied to the output terminal dout2 and applies it to the inversion control terminal of the transfer gate 208. The signal of the output terminal dout2 is applied to the non-inverting control terminal of the transfer gate 208 (or the gate of the NMOS transistor N21), and the inverter I21 is applied to the inverting control terminal (or gate of the PMOS transistor P21). The output signal of is applied. The input terminal of the transfer gate 208 is connected to the node dp2 and the output terminal is connected to the node pp0. The input terminal of the inverter I22 is connected to the node pp0, and the output terminal is connected to the node pp1. The NOR gate I23 uses the signal of the node dp2 and the signal of the node pp1 as input signals. The inverter I24 inverts the output signal of the NOR gate I23 and applies it to the node pp2, which is input to the gate of the PMOS transistor P12. The feedback low pulse generator 206 has a low level for a predetermined time from immediately after the potential change, when the potential of the sense amplifier output signal saout is changed from the low level to the high level while the enable signal poe is activated. It generates a pulse.
    [21] The feedback high pulse generator 214 includes three inverters I31, I32, and I34, a transfer gate 216, and a NAND gate 133. The inverter I31 inverts the signal applied to the output terminal dout2 and applies it to the non-inverting control terminal of the transmission gate 216. The output signal of the inverter I31 is applied to the non-inverting control terminal of the transfer gate 216 (or the gate of the NMOS transistor N31), and the output terminal dout2 is applied to the inverting control terminal (or gate of the PMOS transistor P31). ) Is applied. The input terminal of the transmission gate 216 is connected to the node dn2, and the output terminal is connected to the node nn0. The input terminal of the inverter I32 is connected to the node nn0, and the output terminal is connected to the node nn1. The NAND gate I33 uses the signal of the node dn2 and the signal of the node nn1 as input signals. The inverter I34 inverts the output signal of the NAND gate I33 and applies it to the node nn2, which is input to the gate of the NMOS transistor N12. The feedback high pulse generator 214 has a high level for a predetermined time from immediately after the potential is changed, when the potential of the sense amplifier output signal saout is changed from the high level to the low level while the enable signal poe is activated. It generates a pulse.
    [22] Hereinafter, the operation of the output buffer circuit 200 will be described in detail with reference to FIGS. 3 to 4. 3 is a voltage waveform diagram of the circuit of FIG. 1, and FIG. 4 is a voltage waveform diagram of the circuit of FIG. 2. When the sense amplifier output signal saout is low level or the enable signal poe is low level, a high level signal is applied to the node dp2 via the high level signal path 202, so that the PMOS transistor P11 is turned on. It is turned off and a low level signal is applied to the node pp1. Accordingly, since the NOR gate I23 outputs a low level signal, the high level signal is applied to the node pp2, and the PMOS transistor P12 is also turned off. Then, when the enable signal poe becomes high level and is activated, when a high level sense amplifier output signal saout comes in, a low level signal is applied to the node dp2 through the high level signal path 202. When the low level signal is applied to the node dp2, the PMOS transistor P11 is turned on, so the signal of the output terminal dout2 goes to the high level. At this time, since the transmission gate 208 does not connect the node dp2 and the node pp0 until the signal applied to the output terminal dout2 goes high enough, the node pp1 remains at the low level. . Therefore, when the node dp2 is changed to the low level, the NOR gate I23 outputs a high level, and thus a low level signal is applied to the node pp2, thereby turning on the PMOS transistor P12. When the PMOS transistors P11 and P12 are turned on, the output terminal dout2 starts to pull up to the power supply voltage Vcc. When the output terminal dout2 is sufficiently high, the transfer gate 208 connects the node dp2 and the node pp0, so that the low level signal of the node dp2 is applied to the node pp0. Since the inverter I22 inverts the low level signal applied to the node pp0 and applies the high level signal to the node pp1, the NOR gate I23 outputs the low level signal, and the inverter I24. ) Is inverted to a high level and applied to the gate of the PMOS transistor P12, so that the PMOS transistor P12 is turned off.
    [23] That is, the output signal of the feedback low pulse generator 208 changes to a low level at about the same time when the node dp2 changes to a low level, and changes to a high level when a sufficient high level signal is applied to the output terminal dout2. It will generate a pulse. The low pulse generated by the feedback low pulse generator 208 controls the PMOS transistor P12 so that the PMOS transistor is activated when the enable signal poe is activated and the sense amplifier output signal saout of the high level is applied. When P12 is turned on and a sufficient high level signal is applied to the output terminal dout2, the PMOS transistor P12 is turned off.
    [24] When the enable signal poe becomes high level and is activated when the sense amplifier output signal saout is at the low level, a high level signal is applied to the node dn2 through the low level signal path 210, so that the NMOS transistor N11 is turned on. At this time, since a high level signal is applied to the node nn1, the NAND gate I33 outputs a low level signal, and this signal is inverted by the inverter I34, so that the node nn2 has a high level. A signal is applied to turn on the NMOS transistor N12. When the NMOS transistors N11 and N12 are turned on, the output terminal dout2 starts to pull down to the ground voltage Vss. When the output terminal dout2 is sufficiently low, the transmission gate 216 connects the node dn2 and the node nn0, so that the high level signal of the node dn2 is applied to the node nn0. Since the inverter I32 inverts the high level signal applied to the node nn0 and applies a low level signal to the node nn1, the NAND gate I33 outputs a high level signal, and the inverter I34. ) Inverts it to a low level and applies it to the gate of the NMOS transistor N12, so that the NMOS transistor N12 is turned off.
    [25] That is, the output signal of the feedback high pulse generator 216 changes to a high level almost simultaneously when the node dn2 changes to a high level, and changes to a low level when a sufficient low level signal is applied to the output terminal dout2, resulting in a high level. It will generate a pulse. The high pulse generated by the feedback high pulse generator 216 controls the NMOS transistor N12 so that the instantaneous NMOS transistor is activated when the enable signal poe is activated and a low level sense amplifier output signal saout is applied. When N12 is turned on and a low level signal is applied to the output terminal dout2, the NMOS transistor N12 is turned off.
    [26] When comparing the low-to-high speeds of the output terminal (dout1 of FIG. 1) and the output terminal (dout2 of FIG. 2) in FIGS. 3 and 4, the 43.5ns and 42.9ns, respectively, Comparing the high-to-low speed, it can be seen that the speed of the output buffer circuit 200 according to the present invention is 90.5ns and 90.2ns, respectively, as compared with the conventional output buffer circuit 100. have. FIG. 5 is a current waveform diagram at an output terminal of the circuit of FIG. 1, and FIG. 6 is a current waveform diagram at an output terminal of the circuit of FIG. In FIG. 5, the current waveform 501 is a current flowing through the NMOS transistor N1 of FIG. 1, and an average current value for 50 ns is 3.4 mA. The current waveform 503 is a current flowing through the PMOS transistor P1, and the average current value for 50 ns is 2.8 mA. In FIG. 6, the current waveform 601 is a current flowing through the NMOS transistors N11 and N12, and the average current value for 50 ns is 3.1 mA. The current waveform 603 is a current flowing through the PMOS transistors P11 and P12, and the average current value for 50 ns is 2.5 mA. Through this, it can be seen that the current in the output buffer circuit 200 according to the present invention is about 10% smaller than the conventional output buffer circuit 100. As a result, when 16 I / Os simultaneously perform read operations, noise may be generated due to a high current, thereby preventing malfunction of the semiconductor memory device.
    [27] The embodiments described herein are merely intended to enable those skilled in the art to easily understand and practice the present invention, and are not intended to limit the scope of the present invention. Therefore, those skilled in the art should note that various modifications and changes are possible within the scope of the present invention. The scope of the invention is defined in principle by the claims that follow.
    [28] According to the configuration of the present invention as described above, the current flowing through the pull-up PMOS transistor and the pull-down NMOS transistor can be reduced by about 10% while maintaining the driving speed as compared with the conventional output buffer circuit. As a result, when 16 I / Os simultaneously perform a READ operation, noise may be generated due to a high current, thereby preventing malfunction of the semiconductor memory device.
    权利要求:
    Claims (5)
    [1" claim-type="Currently amended] In the output buffer circuit,
    A first PMOS transistor connected to a power supply terminal, a drain connected to an output terminal of the output buffer circuit, and turned on when a high level signal is input to an input terminal of the output buffer circuit;
    A first NMOS transistor connected to a ground terminal, a drain connected to an output terminal of the output buffer circuit, and turned on when a low level signal is input to an input terminal of the output buffer circuit;
    A low pulse generator for generating a low pulse for a predetermined period immediately after the high level signal is received, when a high level signal is received at an input terminal of the output buffer circuit;
    A high pulse generator for generating a high pulse for a predetermined period immediately after the low level signal is received, when a low level signal is received at an input terminal of the output buffer circuit;
    A second PMOS transistor having a source connected to a power supply terminal, a drain connected to a drain of the first PMOS transistor, and a gate applied with an output signal of the low pulse generator;
    A source is connected to the ground terminal, a drain is connected to the drain of the first NMOS transistor, and a gate of the second NMOS transistor to which the output signal of the high pulse generator is applied.
    And an output buffer circuit.
    [2" claim-type="Currently amended] The method of claim 1,
    The low pulse generator
    A first inverter for inverting a signal applied to the drain of the first PMOS transistor;
    An input terminal is connected to a gate of the first PMOS transistor, a non-inverting control terminal is connected to a drain of the first PMOS transistor, and an inversion control terminal is connected to an output terminal of the first inverter;
    A second inverter for inverting the output signal of the first transfer gate;
    First logic means for performing an OR operation on an output signal of the second inverter and a signal applied to a gate of the first PMOS transistor, and outputting an operation result as an output signal of the low pulse generator;
    And an output buffer circuit.
    [3" claim-type="Currently amended] The method according to claim 1 or 2,
    The high pulse generator is
    A third inverter for inverting a signal applied to the drain of the first NMOS transistor;
    An input terminal is connected to a gate of the first NMOS transistor, an inversion control terminal is connected to a drain of the first NMOS transistor, and a non-inverting control terminal is connected to an output terminal of the first inverter;
    A fourth inverter for inverting the output signal of the second transfer gate;
    Second logic means for performing an AND operation on an output signal of the fourth inverter and a signal applied to a gate of the first NMOS transistor, and outputting an operation result as an output signal of the high pulse generator;
    And an output buffer circuit.
    [4" claim-type="Currently amended] The method of claim 1,
    And the first PMOS transistor is a PMOS transistor of a relatively small size.
    [5" claim-type="Currently amended] The method according to claim 1 or 4,
    And the first NMOS transistor is an NMOS transistor of a relatively small size.
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    同族专利:
    公开号 | 公开日
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2002-01-07|Application filed by 주식회사 하이닉스반도체
    2002-01-07|Priority to KR1020020000713A
    2003-07-16|Publication of KR20030060176A
    优先权:
    申请号 | 申请日 | 专利标题
    KR1020020000713A|KR20030060176A|2002-01-07|2002-01-07|An output buffer circuit|
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